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Standard Cell Design Methodology & Flow Engineer

Apple· Hardware
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Hybrid (Santa Clara, California)$144.6k - $263.8kFull-timePosted 3d ago

About the role

Role focused on standard cell library design, methodology, and flow engineering within a processor design effort. Interface with CAD teams and foundry, develop and automate flows, verify digital blocks, and apply data analysis/ML to circuit timing, power, and area trends.

Responsibilities

  • Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements.
  • Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows
  • Implement sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification.
  • Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect quality issues in large datasets.

Qualifications

  • BS and a minimum of 3 years of relevant industry experience
  • At least 5+ years in Library Characterization, Timing/Power/CCS Noise/Variation Modeling, Liberty Formats, Spice simulation, Static Timing and Power Analysis flows, etc.
  • Experience with timing modeling of large custom macros and complex sequential flops.
  • Exposure to Design For Test, scan concept and write DFT friendly RTL
  • Understands all aspects of implementation specification, design, timing, power, and flow automation.
  • Data analysis and ML knowledge to study data trend and perform QA on big dataset with automation
  • Flow automation skills in standard cells development and integration to improve execution efficiency. Experience of using Python/TCL/Perl
  • Knowledge of FE modeling/Verilog and/or VHDL, and experience with various EDA tools for characterization, synthesis, place-route, Verilog simulation, spice simulation, formal verification, DRC/LVS, RC extraction and/or library characterization.
  • Proven understanding of device physics and process.
  • Familiar with foundry ecosystem and benchmarking practice.

Skills

Required:Verilog/SystemVerilogPythonTCL/PerlEDA Tools (RF/RC extraction, DRC/LVS, Spice, Synthesis, Place-Route)
Nice to have:Machine Learning

Benefits

  • Comprehensive medical and dental coverage
  • retirement benefits
  • discounted products and free services
  • reimbursement for certain educational expenses including tuition
  • discretionary bonuses or commission payments and relocation eligibility
  • Apple employee stock programs and stock purchase plan
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Apple

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