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SOC Design Verification Engineer

Apple· Hardware
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Hybrid (Sunnyvale, California), Hybrid (Irvine, California), Hybrid (San Diego, California)$184.7k - $324.8kPosted 3d ago

About the role

Wireless SOC Design Verification Engineer responsible for pre-silicon RTL verification across block, subsystem, and top-level SOC, developing reusable testbenches, verification environments, and employing metric-driven methodologies to verify IPs/subsystems, power management, wireless interfaces, and full SOC integration.

Responsibilities

  • Partner with architects and designers early to build detailed verification plans from specifications — before RTL lands, not after.
  • Develop reusable block/IP and subsystem-level UVM testbenches, and support IP integration into the SOC.
  • Write directed and constrained-random tests; create and analyze coverage models and drive coverage closure.
  • Debug failures, including corner cases, and manage bug tracking through resolution.
  • Verify low-power design intent using UPF within your scope.
  • Verify end-to-end WiFi and Bluetooth traffic flows from subsystem level up through top-level SOC integration.
  • Apply formal verification where it fits — the team will help you ramp up.
  • Build and improve automated regression flows and contribute to methodology in your area.
  • Explore and apply AI-assisted verification techniques to improve team productivity.
  • Participate in verification reviews and uphold high coding-quality standards.
  • Support post-silicon bring-up as needed.

Qualifications

  • BS and a minimum of 10 years relevant industry experience.
  • Hands-on experience across the verification cycle: test planning, testbench implementation, test creation and debug, and coverage closure.
  • Strong SystemVerilog and Verilog skills, with solid working knowledge of UVM.
  • Solid problem-solving and debugging skills with constrained-random verification.
  • Understanding of digital logic design, SOC architecture, and microarchitecture.
  • Experience taking at least one ASIC/SOC from concept through tape-out.
  • Verification experience with PCIe, bus fabric/NOC, or AHB/AXI-based architectures in a UVM environment.
  • Experience verifying IP or top-level integration for a WiFi or Bluetooth SOC, or knowledge of wireless protocols.
  • Experience with low-power verification, UPF, boot-up, power-cycling, and HW/FW interaction.
  • Experience with SystemVerilog Assertions (SVA) and/or formal tools (e.g., JasperGold).
  • Experience defining coverage space and writing coverage models.
  • Experience with embedded CPU verification; programming in C/C++ or assembly.
  • Scripting in Python or Perl; interest in applying AI/ML to verification workflows.
  • Great teammate with excellent communication skills and the desire to take on diverse challenges.

Skills

Required:SystemVerilogVerilogUVMLow-power verificationUPFCoverage modelingASIC/SoC tape-out
Nice to have:Formal verificationEmbedded CPU verificationPython/Perl scripting

Benefits

  • Base pay range: $184,700 - $324,800 (USD annually).
  • Discretionary employee stock programs, including RSUs and Employee Stock Purchase Plan.
  • Comprehensive medical and dental coverage, retirement benefits, discounted products and free services.
  • Educational expense reimbursement for career advancement; potential for discretionary bonuses or relocation.
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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