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Design Verification Engineer

Apple· Hardware
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Hybrid (Herzliya, Tel Aviv District)Full-timePosted 3d ago

About the role

In this role, responsible for defining DV methodologies, test-bench infrastructure, and project execution for next-generation Apple high-speed interfaces to enable I/O connectivity solutions. Collaborates with Architecture, Design and SW teams to influence future products and accelerate verification time, with involvement in Post-Silicon Validation.

Responsibilities

  • Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors
  • Apply advanced techniques to achieve verification with the highest quality, productivity, and time-to-market
  • Work closely with the design team to ensure timely delivery of quality designs
  • Work with methods to accelerate verification time
  • Involvement in Post-Silicon Validation

Qualifications

  • 6+ years of experience in SoC Verification
  • Advanced knowledge of SoC architecture/design, verification flows, and broad system view
  • Deep understanding and experience in advanced verification processes (dynamic, coverage-based, and formal methods)
  • Extensive experience with System Verilog or UVM
  • Experience with verification infrastructure development
  • Scripting and programming experience using Perl, Python, Verilog, SystemVerilog, C, C++, and TCL (advantage)
  • B.Sc / M.Sc in Electrical or Computer Engineering

Skills

Required:SoC VerificationSystemVerilog/UVMVerification infrastructure developmentScripting languages (Perl, Python, TCL, etc.)
Nice to have:Languages
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Apple

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

Discover the innovative world of Apple and shop everything iPhone, iPad, Apple Watch, Mac, and Apple TV, plus explore accessories, entertainment, and expert device support.

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