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Design Verification Engineer

Apple
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Haifa, HerzliyaPosted 3d ago

About the role

Role responsible for defining DV methodologies, test-bench infrastructure, and project execution for next-generation Apple high-speed interfaces, enabling advanced I/O connectivity solutions. Collaborates with Architecture, Design, and SW teams, develops verification plans, tools, test benches, monitors, and high-coverage stimuli. Involves post-silicon validation and acceleration of verification time.

Responsibilities

  • Define DV methodologies, test-bench infrastructure, and project execution for next-generation Apple high-speed interfaces.
  • Develop verification test plans, tools, test benches, protocol monitors, and high-coverage stimulus vectors.
  • Apply advanced verification techniques to achieve high quality, productivity, and faster time-to-market.
  • Work closely with the design team to ensure timely delivery of quality designs.
  • Work with methods to accelerate verification time.
  • Involvement in Post-Silicon Validation.

Qualifications

  • 6+ years of experience in SoC Verification
  • Advanced knowledge of SoC architecture/design, verification flows, and broad system view
  • Deep understanding and experience in advanced verification processes (dynamic, coverage-based, and formal methods)
  • Extensive experience with SystemVerilog or UVM
  • Experience with verification infrastructure development
  • Scripting and programming experience using Perl, Python, Verilog, SystemVerilog, C, C++, and TCL – an advantage
  • B.Sc / M.Sc in Electrical or Computer Engineering

Skills

Required:SoC VerificationSystemVerilog / UVMVerification infrastructure development
Nice to have:Scripting / Programming
Last updated Oct 23, 2026. Interested? Apply on the company site.

About Apple

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