Network Engineer - ML Infrastructure (High-Speed Interconnects)
xAI· Infrastructure
Palo Alto, CA$180k - $440kFull-timePosted 8mo ago
About the role
ML Infrastructure Engineer focused on high-speed interconnects to enable large-scale AI training and inference clusters. Design, build, and optimize copper and optical interconnects (200G+ SerDes, PAM4) across data centers, with emphasis on performance, power efficiency, and reliability for AI/ML workloads.
Responsibilities
- Design, validate, and productize high-speed copper and optical connectivity solutions for AI clusters (100k+ GPU scale).
- Own vendor due diligence and onboarding for new 1.6T products including AEC and pluggable optical transceivers (DR4/8, FR4) including rigorous bring-up & characterization.
- Investigate the opportunity for LPO and LRO in our network.
- Evaluate early co-packaged and near-packaged engines for switches and GPUs.
- Pathfinding for new interconnect modalities including VCSEL, microLED, THz radio-based solutions to improve network economics and reliability.
- Work closely with vendors (transceiver, cable, SerDes, DSP, silicon photonics foundries) to influence roadmaps and ensure timely delivery of next-gen solutions.
- Collaborate with ML training teams to translate workload communication patterns into concrete interconnect topology and optical reconfigurability requirements.
- Perform system-level simulation of end-to-end fabric performance.
- Drive failure analysis, root cause, and corrective actions for interconnect-related issues in production clusters through fleet-level metrics gathering and analysis.
- Contribute to internal tooling and automation for interconnect health monitoring, telemetry, diagnostics, remediation and automated qualification pipelines.
- Stay current with industry standards (OIF CMIS, IEEE) and emerging technologies (multi-core/hollow-core fiber, 448G SerDes, TFLN, ring resonators)
Qualifications
- At least 8+ years of hands-on experience in designing, deploying and operating high-speed copper and optical interconnects, preferably in a module design role or in a hyperscale datacenter environment.
- Master's or PhD degree in Electrical Engineering, Photonics or Physics.
- Deep knowledge of PAM4 SerDes performance, equalization, jitter, crosstalk.
- Solid operational understanding of FEC, Retimers, TIAs and Drivers.
- Deep knowledge of optical link budget analysis and performance metrics including TDECQ, OMA, Tcode, stressed receiver sensitivity and associated diagnostics.
- Expertise in transceiver components including CW lasers, SiPh PICs, EML, DSP, passive subassemblies, their failure modes and characterization.
- Knowledge of thermal, mechanical, power, signal integrity constraints in dense hardware.
- Knowledge of SiPh design process, yield improvement and reliability testing.
- Familiarity with CPO technologies and challenges/risk areas.
- Familiarity with subcomponent supply chains and global manufacturers, ODMs and CMs.
- Strong problem-solving skills and ability to thrive in a fast-paced, ambiguous setting.
Skills
Required:High-speed copper and optical interconnect designSystem-level simulation
Nice to have:Vendor management & collaboration
Benefits
- equity
- comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- short & long-term disability insurance
- life insurance
- various other discounts and perks
Last updated Oct 14, 2026. Interested? Apply on the company site.
More open roles at xAI
- Supervisor, Child Safety Operations4d agoAustin, TX · Safety
- Security Engineer, Kubernetes4d agoHybrid (Palo Alto, CA; Austin, TX; New York, NY; Washington, DC) · Information Security
- Security Engineer - GRC Sales4d agoInformation Security
- Site Reliability Engineer4d agoHybrid (Memphis/Southaven) · Data Center
- Senior Linux Data Center Technician - Memphis4d agoHybrid (Memphis, TN) · Data Center