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Principal ASIC Design Engineer (Starshield)

SpaceX· Starshield Satellite Engineering
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Hawthorne, CA$200k - $285kfull-timePosted 6mo ago

About the role

ASIC/FPGA design engineer role on SpaceX Starshield team focused on developing advanced FPGAs/ASICs for space and ground infrastructure to support national security initiatives.

Responsibilities

  • Design digital ASICs and/or FPGAs for Starshield projects.
  • Evaluate architectural trade-offs based on features, performance requirements and system limitations. Derive specifications for the subsystems and circuits, and work with modem/DSP and RFIC engineers to partition functions between hardware and software domains.
  • Define micro-architecture, implement the RTL in Verilog/SystemVerilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design.
  • Work closely with verification team to ensure all aspects of the design are covered and verified.
  • Provide timing constraints for those IPs and support the physical implementation team (synthesis, timing closure, formality check).
  • Participate in silicon bring-up and validation. Assist in the development of automated test lab equipment for lab measurements.

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science.
  • 8+ years of experience in RTL implementation and/or FPGA/ASIC development.

Skills

Required:RTL designVerilog/SystemVerilogDigital design beyond RTLVerification collaborationTiming and physical implementation
Nice to have:ScriptingEDA toolsASICS/embedded processors

Benefits

  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • Short and long-term disability insurance
  • Life insurance
  • Paid parental leave
  • Paid vacation and holidays
  • Employee stock options or long-term incentives
  • Discounts and perks
Last updated Jul 8, 2026. Interested? Apply on the company site.

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