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Sr. Full Chip Physical Verification Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Austin, TXfull-timePosted 5mo ago

About the role

Senior full-chip physical verification engineer at SpaceX, focusing on DRC/LVS/ESD/PERC signoff, flow development for advanced nodes, and tapeout readiness for Starlink silicon.

Responsibilities

  • Own and execute full-chip DRC, LVS, ESD, PERC and antenna signoff using industry standard tools like Calibre, ICV, or Pegasus
  • Develop, maintain, and optimize physical verification flows for advanced node SoC’s.
  • Interpret and implement foundry DRM — translate rule updates into verified flow changes
  • Debug and resolve complex DRC/LVS violations across hierarchical full-chip designs
  • Perform ESD verification — validate protection strategies, current paths, and CDM/HBM compliance
  • Drive tapeout readiness by coordinating signoff across block and top-level and Hard IP design teams
  • Engage directly with foundry teams to resolve DRM ambiguities and waiver requests.
  • Develop/modify design flows as needed to meet the overall design quality of results and chip integration requirements.Leverage AI agents to automate rule deck validation, violation triage, and signoff reporting workflows

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

Skills

Required:Duties related to physical verification (DRC/LVS/ESD/PERC)CalibreIC Validator (ICV)DRM interpretation
Nice to have:PegasusAdvanced node experience
Last updated Jul 8, 2026. Interested? Apply on the company site.

About SpaceX

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