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Principal Design Verification Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Redmond, WA$210k - $335kFull-timePosted 5mo ago

About the role

Principal Design Verification Engineer responsible for digital ASIC/FPGA verification, leading verification test plans, and contributing to pre-silicon, bring-up, and post-silicon validation for SpaceX Starlink ASICs.

Responsibilities

  • Responsible for digital ASIC and/or FPGA verification at block and system level
  • Lead and execute verification test plan, development, and milestones from beginning to end
  • Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
  • Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or computer science
  • 10+ years of experience with design verification and test bench development
  • 10+ years of experience with design verification and test bench development

Skills

Required:Design verification methodologies (UVM/OVM/VMM)
Nice to have:Object-oriented programmingConstrained random verificationTest plan development and coverage modelingPython scripting for automationRTL design, chip bring-up, post-silicon validation

Benefits

  • comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • short & long-term disability insurance
  • life insurance
  • paid parental leave
  • 3 weeks of paid vacation & 10+ paid holidays per year
  • sick leave and various other discounts and perks
  • potential discretionary bonuses and stock/options via long-term incentives
  • Employee Stock Purchase Plan
Last updated Aug 26, 2026. Interested? Apply on the company site.

About SpaceX

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