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Sr. ASIC DFT Engineer (Silicon)

SpaceX· Silicon Engineering
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Austin, TXfull-timePosted 4mo ago

About the role

Senior ASIC DFT engineer at SpaceX, focused on developing and validating DFT architectures and test methodologies for next-generation ASICs used in Starlink space/ground infrastructure.

Responsibilities

  • Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
  • Integration and verification of Design for Test (DFT) IPs and fabrics within Subsystems
  • Set up and run Automatic Test Pattern Generation (ATPG) tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, while focusing on pattern compression, diagnosis, and hierarchical test flows
  • Run and debug non-timing and SDF annotated gate-level simulations
  • Create and validate DFT patterns for post-silicon bringup and also help with ATE debug through all cycles of silicon characterization
  • Develop test scripts, automate processes, and analyze data using programming languages such as Perl, Python, Tcl, or C++

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering, or physics
  • 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing

Skills

Required:DFT architecture implementationIP integration and verificationATPGgate-level simulationScripting/programming

Benefits

  • (not specified in the description)
Last updated Jul 8, 2026. Interested? Apply on the company site.

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