Sr. ASIC DFT Engineer (Silicon)
SpaceX· Silicon Engineering
Irvine, CA$165k - $260kfull-timePosted 4mo ago
About the role
Senior ASIC DFT Engineer responsible for implementing and optimizing DFT architectures, integrating DFT IPs, performing ATPG and post-silicon bringup activities, and developing test automation for SpaceX Starlink silicon products.
Responsibilities
- Implement and optimize DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools
Qualifications
- Bachelor’s degree in electrical engineering, computer engineering, or physics
- 5+ years of experience in semiconductor Design For Test (DFT) engineering, post-silicon validation, and/or production testing
Skills
Required:DFT architecture design and optimizationATPG and pattern generationDFT integration and verificationScripting and automationCross-functional collaboration
Nice to have:Post-silicon bringup and ATE debugging
Benefits
- comprehensive medical, vision, and dental coverage
- 401(k) retirement plan
- short and long-term disability insurance
- life insurance
- paid parental leave
- 3 weeks of paid vacation
- 10+ paid holidays per year
- paid sick leave
- Employee Stock Purchase Plan and potential stock-based incentives
Last updated Jul 8, 2026. Interested? Apply on the company site.
About SpaceX
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