← All roles

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
Apply on company site
Austin, TXFull-timePosted 4mo ago

About the role

Senior SOC/ASIC Physical Design Engineer to develop cutting-edge silicon for SpaceX Starlink infrastructure, collaborating with ASIC teams to drive architectural feasibility, timing, power/area targets, and robust signoff through physical design flows.

Responsibilities

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

Skills

Required:ASIC/SoC RTL2GDSII physical design and signoff flowsIndustry standard EDA toolsFinFET/CMOS physicsCMOS digital design principles
Nice to have:CMOS power dissipationCMOS analog circuit designDFT/Scan/MBIST/LBISTScripting
Last updated Jul 8, 2026. Interested? Apply on the company site.

About SpaceX

defense-aero-and-safetysetter-30setter-30-2026-q1wing-list-2026wing-list-2026-giga-stage
Company profileWebsite

More open roles at SpaceX