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Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Irvine, CA$165k - $260kfull-timePosted 4mo ago

About the role

Senior SOC/ASIC Physical Design Engineer responsible for partition synthesis, physical implementation, signoff, and collaboration with ASIC design teams to drive architectural feasibility and design targets for Starlink-related silicon.

Responsibilities

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

Skills

Required:ASIC/SOC RTL2GDSII physical design and signoff flowsEDA toolsFinFET/CMOS physicsCMOS digital design principles
Nice to have:CMOS power/leakageCMOS analog circuit knowledgeDFT/Scan/MBIST/LBISTScripting

Benefits

  • comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • short & long-term disability insurance
  • life insurance
  • paid parental leave
  • vacation and holidays
  • sick leave
  • equity/stock options and/or long-term incentives
  • employee stock purchase plan
Last updated Jul 8, 2026. Interested? Apply on the company site.

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