Senior Validation & SI Correlation Engineer
SambaNova· Hardware
San Jose, CA$210k - $280kFull-timePosted 3mo ago
About the role
Senior hardware validation and signal integrity (SI) engineer focused on validating high-speed interfaces and power/controls in AI server systems. Combines SI modeling, system-level electrical validation, and test methodology with automation to bridge simulation and silicon in next-generation AI infrastructure.
Responsibilities
- Drive correlation between pre- and post-layout SI simulations and physical lab measurements across PCIe Gen5/6, DDR5, and 112G/224G Ethernet.
- Develop and refine EM models for PCB discontinuities, high-speed connectors, and vias using Ansys HFSS, Cadence Sigrity, or equivalent tools.
- Investigate discrepancies due to manufacturing tolerances, material properties, or de-embedding inaccuracies.
- Lead validation of housekeeping and control buses (I2C, SPI, eSPI, UART, SMBus) ensuring protocol compliance and robust timing margins.
- Validate power-on/off sequences and correlate VR control loop simulations with physical transient response and ripple measurements.
- Ensure reliable operation of sideband signals, reset logic, and BMC hardware interfaces under AI workloads.
- Collaborate with SI, PI, and Firmware teams to resolve system-hang and link-training failures rooted in electrical noise or power instability.
- Author Hardware Validation Plans (HVP) with full coverage of critical electrical test points.
- Build Python-based automation scripts to drive data collection from VNAs, BERTs, and oscilloscopes to accelerate validation throughput and repeatability.
Qualifications
- B.S. or M.S. in Electrical Engineering (M.S. preferred).
- 10+ years of experience in high-speed digital design or hardware validation within a data center, systems architecture, or server bring-up environment.
- Expert-level proficiency in SI/EM tools: Ansys HFSS/SIwave, Cadence Sigrity/Allegro, or Keysight ADS.
- Hands-on mastery of high-bandwidth real-time oscilloscopes, VNAs, and logic analyzers.
- Deep knowledge of high-speed protocol physical layers (PCIe, IEEE 802.3) and low-speed control buses (I2C, SPI).
- Strong fundamentals in digital circuit design, debug, and computer architecture.
- Familiarity with power and thermal challenges of high-density AI clusters—including 48V power delivery and high di/dt transients.
- Programming fluency in Python or equivalent scripting languages (Perl, Shell).
- PCIe Gen5/6 and 100G Ethernet expertise.
Skills
Required:SI/EM toolsHigh-speed measurementHigh-speed interfacesProgrammingPower integrity
Benefits
- Base Salary Range: $210,000—$280,000 USD annual
Last updated Sep 13, 2026. Interested? Apply on the company site.
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