← All roles

RTL Design Engineer – Interconnect & Network Datapath

OpenAI· Scaling
Apply on company site
Hybrid (San Francisco)$225k - $445k + equityFull-timePosted 3mo ago

About the role

Senior RTL design engineer focused on on-chip interconnect and off-chip networking datapaths for OpenAI’s custom AI accelerator platform. Responsible for microarchitecture, SystemVerilog implementation, verification, and production readiness of packet-based interconnect components and NoC fabrics, with leadership across teams and external partners.

Responsibilities

  • Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol adapters, arbiters, queues, schedulers, buffers, and traffic-management logic.
  • Design mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring.
  • Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems.
  • Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work.
  • Collaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic workloads.
  • Work with verification teams to develop coverage plans, assertions, stress scenarios, and debug strategies for highly concurrent packet and fabric behavior.
  • Partner with physical design teams on floorplan-aware design, pipeline strategy, timing closure, power, area, and physical congestion.
  • Collaborate with firmware, software, validation, and post-silicon teams through bring-up and production readiness.
  • Drive third-party engagements involving networking, interface protocols, and silicon IP while maintaining design quality and execution accountability.
  • Provide technical leadership through architecture and design reviews, documentation, mentoring, and reusable RTL methodologies.

Qualifications

  • Extensive industry experience with recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL.
  • Demonstrated networking expertise in one or more of the following: Ethernet switching, NIC/SmartNIC/DPU datapaths, network accelerators, RDMA/RoCE, InfiniBand, traffic management, or custom scale-up/scale-out transports.
  • Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
  • A strong record of owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up.
  • Experience designing queues, arbiters, schedulers, buffers, routing logic, virtual channels, credit-based flow control, congestion management, quality of service, ordering, or deadlock-avoidance mechanisms.
  • Experience with on-chip, chip-to-chip, or host interfaces such as AXI, CHI, CXL, PCIe, or Ethernet, alongside deeper networking or packet-datapath expertise.
  • Experience designing custom networking protocols, protocol extensions, or hardware datapaths for large-scale RDMA/RoCE, HPC, or AI systems.
  • Strong familiarity with RTL development and signoff flows (lint, CDC/RDC, synthesis, formal verification, static timing analysis, power analysis, design-for-test).
  • Experience collaborating with architecture, verification, physical design, firmware, performance, and post-silicon teams to deliver complex silicon.
  • Strong judgment balancing performance, power, area, schedule, verification risk, and physical implementation constraints.
  • Ability to provide technical direction, mentor engineers, and drive alignment while remaining actively involved in RTL design and debugging.
  • Passion for reducing complexity and improving engineering leverage through automation and pragmatic design.

Skills

Required:RTL design in SystemVerilogMicroarchitectureNetworking protocols and datapathsVerification and debuggingPerformance optimizationCollaboration across functions

Benefits

  • Medical, dental, and vision insurance with employer contributions to Health Savings Account
  • Pre-tax Health FSA, Dependent Care FSA, and commuter expenses
  • 401(k) retirement plan with employer match
  • Paid parental leave (up to 24 weeks for birth parents, 20 weeks for non-birth parents) + paid medical and caregiver leave (up to 8 weeks)
  • Paid time off: flexible PTO for exempt, up to 15 days annually for non-exempt
  • 13+ paid company holidays and additional paid office closures
  • Mental health and wellness support
  • Employer-paid basic life and disability coverage
  • Annual learning and development stipend
  • Daily meals in offices and meal delivery credits
  • Relocation support for eligible employees
  • Additional taxable fringe benefits (e.g., charitable donation matching, wellness stipends)
Last updated Sep 10, 2026. Interested? Apply on the company site.

About OpenAI

ai-infrastructure-and-developmentliquid-ai-recruiting-targetllmsetter-30setter-30-2026-q1speech-to-texttext-to-speechvoice-ai-stack
Company profileWebsite

More open roles at OpenAI