ASIC Technical Program Manager
San JoseFull-timePosted 3mo ago
About the role
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across prefill and decode workloads, with a focus on inference. The role involves hands-on, high-accountability program management across ASIC development cycles, coordinating Physical Design, DFT, DV, and RTL teams, and managing external vendor relationships.
Responsibilities
- Cross-Functional Technical Coordination: Own program management across Physical Design, DFT, DV, RTL, and Post-Silicon teams. Understand inter-team dependencies - know who owns what, when handoffs need to happen, and what needs to be signed off before downstream work can begin (e.g., RTL version gates for synthesis, DFT insertion checkpoints, ECO cycles).
- Vendor Management: Engage directly with external vendors, including EDA partners and implementation partners. Hold vendors accountable to timelines and deliverables. Be prepared to push back, defend Etched’s technical requirements, and escalate when needed.
- Risk Identification and Mitigation: Proactively surface critical path risks, schedule slippage, and cross-team blockers. Develop mitigation strategies in partnership with engineering leads and escalate appropriately to technical and executive stakeholders.
- Project Planning and Execution: Manage the scheduling and execution of complex, multi-team hardware programs. Keep projects on track across tape-out milestones, synthesis respins, and signoff cycles.
- Stakeholder Communication: Provide regular, clear updates to engineering leads, VP-level stakeholders, and executive leadership on project status, risks, and decisions required. Set the tone for meetings, facilitate alignment, mediate technical disagreements, and drive to decisions.
- Process Coordination: Work with ops and engineering teams to maintain accurate tracking of program state, action owners, and open items. Support the adoption of tooling and dashboards that improve engineering visibility.
- Technical Acumen: Bring enough ASIC domain knowledge to communicate credibly with engineers across the design stack and with external partners. You don’t need to be a designer, but you need to know the difference between a .3 and .5 RTL release, understand where DFT fits in the flow, and have a feel for what a synthesis restart actually involves.
Qualifications
- At least one full ASIC tape-out under your belt.
- Solid understanding of the RTL-to-GDSII flow, including where Physical Design, DFT, DV, and RTL teams intersect and hand off to each other.
- 5+ years of experience in technical program management, engineering program management, or a closely related role within the semiconductor or hardware space.
- Experience working directly with external EDA vendors or implementation partners.
- Exceptional follow-through and proactivity.
- Strong communication and facilitation skills.
- Comfort with fast-paced, ambiguous startup environments where priorities shift and programs evolve quickly.
- Bachelor’s degree in Engineering, Computer Science, or a related field.
Skills
Required:ASIC tape-out experienceRTL-to-GDSII flow understanding
Benefits
- Medical, dental, and vision packages with generous premium coverage
- $500 per month credit for waiving medical benefits
- Housing subsidy of $2.5k per month for those living within walking distance of the office
- Relocation support for those moving to San Jose (Santana Row)
- Various wellness benefits covering fitness, mental health, and more
- Daily lunch and dinner in our office
- Unlimited compute budget subject to ROI justification
Last updated Sep 17, 2026. Interested? Apply on the company site.
About Etched
Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.
frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
More open roles at Etched
- Research Engineer, RL Frontiers4d agoSan Jose · Software
- Internal Acceleration, Research Engineer (Hardware)4d agoSan Jose · Software
- Internal Acceleration, Research Engineer (Kernels)4d agoSan Jose · Software
- Internal Acceleration, Engineer (Kernels)4d agoSan Jose · Software
- Internal Acceleration, Engineer (ASIC)4d agoSan Jose · Software