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Design Verification Engineer - Internal IP

Etched· ASIC
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Austin$150k - $350kFull-timePosted 3mo ago

About the role

Design Verification Engineer to join Etched's Internal IP DV team, focusing on verification of custom IPs powering chips (systolic arrays, DMA engines, NoCs) across the hardware-software stack.

Responsibilities

  • Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
  • Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
  • Debug complex datapath and protocol issues in RTL and testbench environments.
  • Work closely with architects and designers to validate functionality and design intent.
  • Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
  • Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

Qualifications

  • Proficiency with UVM and SystemVerilog.
  • Strong debugging and problem-solving skills for complex digital designs.
  • Solid knowledge of computer architecture and digital design fundamentals.
  • Hands-on experience verifying datapaths, memory systems, interconnects, or high-throughput fabrics.

Skills

Required:UVMSystemVerilogDebuggingComputer architectureDatapath/memory verification

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Unlimited compute budget subject to ROI justification
Last updated Oct 15, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier

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