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DV Intern

Etched· ASIC
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San Jose$0InternPosted 3mo ago

About the role

Design Verification intern focused on verifying custom IPs powering Etched chips (systolic arrays, DMA engines, NoCs) to ensure robustness, high performance, and silicon-readiness. Collaboration across architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack. Spring '27 and Summer '27 internship cohorts.

Responsibilities

  • Verify and validate custom IPs (systolic arrays, DMA engines, NoCs) for robustness, performance, and silicon-readiness.
  • Collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the hardware-software stack.
  • Write and maintain verification test benches, utilize SystemVerilog/UVM/Python as appropriate.
  • Engage in verification work with physical design flows and tooling to understand end-to-end silicon verification.

Qualifications

  • Progress towards a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or related field.
  • Familiarity with high-speed digital logic
  • Exposure to ASIC or SoC design concepts
  • Familiarity with SystemVerilog, UVM, or Python
  • Familiarity with verification work and writing test benches
  • Familiarity with physical design flows and tooling
  • Ability to learn quickly about transformers and aspects of modern artificial intelligence

Skills

Required:SystemVerilogUVMPythonHigh-speed digital logic

Benefits

  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
Last updated Oct 22, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
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