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Design Verification Engineer - Internal IP

Etched· ASIC
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San Jose$150k - $350kFull-timePosted 3mo ago

About the role

Design Verification Engineer to validate custom IPs powering Etched chips (systolic arrays, DMA engines, NoCs) through UVM/SystemVerilog testbenches, verification plans, and cross-team collaboration across RTL, SW/FW/emulation.

Responsibilities

  • Develop and maintain UVM/SystemVerilog testbenches for high-performance IPs (compute arrays, DMAs, NoCs, memory subsystems).
  • Define and execute verification plans covering functional correctness, corner cases, concurrency, and performance bottlenecks.
  • Debug complex datapath and protocol issues in RTL and testbench environments.
  • Work closely with architects and designers to validate functionality and design intent.
  • Partner with SW, FW, and emulation teams to ensure end-to-end bring-up and debug coverage.
  • Contribute to reusable DV infrastructure, coverage models, and methodology improvements.

Qualifications

  • Proficiency with UVM and SystemVerilog.

Skills

Required:UVMSystemVerilogDebugging complex digital designsComputer architecture basicsdatapath/memory system verification
Nice to have:SystemVerilog Assertions (SVA)Scripting for automation

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2.5k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Unlimited compute budget subject to ROI justification
Last updated Oct 15, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
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