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DFT Intern

Etched· ASIC
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San JoseInternPosted 3mo ago

About the role

Internship at Etched focusing on DFT flow automation and verification across frontend and backend design teams, with exposure to MBIST, Scan, BSCAN, SSN simulations and ATPG fault models. Spring '27 and Summer '27 cohorts.

Responsibilities

  • Review and refine DFT flow automation to support chip-level regression on Caelius
  • Contribute to DFT verification (including MBIST, Scan, BSCAN, and SSN simulations)
  • Develop flows for various ATPG fault models
  • Collaborate across frontend and backend design teams

Qualifications

  • Progress towards a Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or a related field
  • Familiarity with a hardware description language (Verilog or SystemVerilog)
  • Exposure to ASIC or SoC design concepts
  • Familiarity with digital logic design fundamentals
  • Familiarity with standard ASIC design flow steps (synthesis, STA, DFT)
  • Familiarity with scripting in Python, Tcl, or another language
  • Ability to learn quickly about transformers and other aspects of modern artificial intelligence

Skills

Required:Verilog/SystemVerilogASIC/SoC design conceptsScripting (Python, Tcl, or similar)
Nice to have:DFT concepts (MBIST, scan insertion, scan compression)ATPG fault models (SAF, TDF, BDF, IDDQ, PDF)

Benefits

  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Direct mentorship from industry leaders and world-class engineers
Last updated Oct 22, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
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