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PD Intern

Etched· ASIC
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San Jose$0InternPosted 3mo ago

About the role

Physical Design intern responsible for realizing front-end designs in silicon, helping to improve iteration speed to final signoff, developing and running Physical Design flows, and advising RTL design decisions. Spring '27 and Summer '27 internship programs.

Responsibilities

  • Assist in developing and running Physical Design flows to synthesize blocks
  • Automate final design checks
  • Advise RTL design decisions
  • Realize front-end designs in silicon
  • Help improve iteration speed to final signoff

Qualifications

  • Progress towards a Bachelor’s, Master’s, or PhD in electrical engineering, computer engineering, or related field
  • Familiarity with high-speed digital logic
  • Exposure to ASIC or SoC design concepts
  • Familiarity with SystemVerilog, UVM, or Python
  • Familiarity with verification work and writing test benches
  • Familiarity with physical design flows and tooling
  • Ability to learn quickly about transformers and other aspects of modern artificial intelligence

Skills

Required:SystemVerilogPython
Nice to have:UVM

Benefits

  • 12-week paid internship
  • Generous housing support for those relocating
  • Daily lunch and dinner in our office
  • Direct mentorship from industry leaders and world-class engineers
Last updated Oct 22, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
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