← All roles

Formal Verification - DV

Etched· ASIC
Apply on company site
San JoseFull-timePosted 3mo ago

About the role

Formal Verification Engineer to join the ASIC Design Verification team at Etched, focusing on formal verification across custom IP, interface IP, and SoC subsystems to prove design correctness and drive verification closure.

Responsibilities

  • Define and drive formal verification strategy across the ASIC DV team for complex IP blocks, interface subsystems, and SoC integration logic.
  • Develop formal verification plans covering functional correctness, connectivity, ordering, reset behavior, configuration legality, and deadlock/livelock freedom.
  • Build reusable formal environments using SystemVerilog Assertions, assumptions, constraints, checkers, cut-points, abstraction models, and reference models.
  • Drive proof convergence using abstractions, cut-points, assume-guarantee reasoning, cover properties, bounded-proof analysis, and coverage metrics to establish formal sign-off confidence.
  • Work with architects and RTL designers to translate design intent and specifications into high-value formal properties and closure criteria.
  • Partner with UVM DV, emulation, software, and firmware teams to align formal verification with simulation, coverage, regressions, and bring-up.
  • Debug complex RTL, protocol, datapath, connectivity, and integration bugs using formal counterexamples, waveforms, and design analysis.
  • Contribute to formal sign-off methodology, regression automation, reporting, and design-for-formal best practices.

Qualifications

  • 5+ years of design verification experience, including significant hands-on formal verification experience on complex digital designs or shipping silicon.
  • Strong proficiency with SystemVerilog, SystemVerilog Assertions, and formal verification methodology.
  • Experience with commercial formal tools such as Cadence JasperGold, Synopsys VC Formal, or Siemens Questa Formal.
  • Strong understanding of digital design, computer architecture, datapaths, interconnects, memory systems, and standard SoC interfaces.
  • Ability to model complex design behavior using assumptions, abstractions, constraints, cut-points, checkers, and reference models.
  • Strong debugging skills across RTL, specifications, formal counterexamples, simulation waveforms, and verification reports.
  • Experience collaborating across architecture, RTL design, UVM DV, emulation, software, firmware, and vendor teams.
  • You thrive in a fast-paced startup environment and can take ownership of ambiguous, high-impact verification problems.

Skills

Required:SystemVerilogFormal verification methodologiesCommercial formal toolsDebugging across RTL and formal artifactsCollaboration across teams
Nice to have:Automation and scripting

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2.5k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
Last updated Sep 17, 2026. Interested? Apply on the company site.
Etched logo

About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
Company profileWebsite

More open roles at Etched