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DFT (Design For Test) Engineer

Etched· ASIC
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San Jose$150k - $350k + equityFull-timePosted 3mo ago

About the role

Design For Testability (DFT) Engineer responsible for ensuring robust testability of ICs from design to production, improving testing efficiency, coverage, yield, and reliability.

Responsibilities

  • Develop and implement robust Design for Test (DFT) architectures for ASIC and SoC designs to enhance test coverage, debug capability, and fault isolation.
  • Integrate industry-standard DFT methodologies such as scan insertion, boundary scan, Built-In Self-Test (BIST), and Memory BIST (MBIST).
  • Collaborate cross-functionally with design and verification teams to ensure DFT requirements are addressed early and consistently throughout the design cycle.
  • Analyze test results and silicon debug data to provide design feedback and drive improvements in coverage, yield, and reliability.
  • Create and execute comprehensive DFT verification plans to validate the correct implementation and functionality of all DFT features.
  • Apply simulation-based and formal verification techniques to ensure high confidence in DFT logic correctness.
  • Conduct internal DFT audits and design reviews to proactively identify and resolve gaps in testability or coverage.
  • Support silicon bring-up, debug, and failure analysis during post-silicon validation to ensure successful product launch.
  • Partner with test engineering teams to develop and optimize Automated Test Equipment (ATE) programs for volume production.
  • Generate production-quality test patterns and ensure robust failure analysis capability in high-volume environments.
  • Collaborate with manufacturing and quality teams to implement data-driven test process improvements and monitor long-term product health.
  • Ensure test strategies are aligned with product milestones, manufacturing timelines, and quality/reliability targets.
  • Author and maintain detailed documentation for DFT architecture, test plans, procedures, and debug guides.
  • Share best practices through training sessions, onboarding, and mentorship to enhance DFT awareness across design and test teams.
  • Stay current with emerging DFT technologies, industry trends, and evolving standards to continually improve internal methodologies.

Qualifications

  • - 10+ years of experience in DFT engineering with a track record of successful test implementations for ASIC or SoC products.
  • - A deep understanding of digital design, verification methodologies, and DFT implementation practices.
  • - Proficiency in System Verilog and fluency with industry-standard EDA tools (e.g., Synopsys DFT Compiler, Cadence Encounter Test, Mentor Tessent).
  • - Scripting and automation experience using Python, Perl, or TCL to streamline DFT implementation and test processes.
  • - Track record of leading DFT initiatives across multiple product generations in high-performance or high-volume silicon environments.
  • - Strong analytical and debugging skills, with the ability to work across teams to resolve complex testability issues.
  • - Excellent communication and collaboration abilities, with a focus on clarity and cross-functional alignment.
  • - A Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field (Master’s preferred).

Skills

Required:Design for Testability (DFT)SystemVerilogEDA ToolsScripting

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2.5k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Unlimited compute budget subject to ROI justification
Last updated Oct 15, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

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