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Design Verification Engineer - Interface IP

Etched· ASIC
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Austin$150k - $350kFull-timePosted 3mo ago

About the role

Design Verification Engineer to join the Interface IP DV team, validating correctness and performance across the hardware-software stack for IP subsystems and interfaces.

Responsibilities

  • End to end ownership of one or more of the following IP subsystems: PCIe, Ethernet, CPU (arc/arm), low power peripherals, sensors
  • Understand vendor IP configurations and handle handshake with internal IP team
  • Develop and maintain UVM/SystemVerilog-based verification environments to ensure functional correctness, performance, and compliance with IP specifications.
  • Collaborate with integration and SoC DV teams to validate seamless interaction of external IPs within the broader chip architecture.
  • Drive coverage closure and sign-off by defining metrics, analyzing gaps, and ensuring comprehensive verification across corner cases and stress scenarios.

Qualifications

  • 5+ years of design verification experience
  • Hands-on experience with industry-standard verification methodologies like SystemVerilog/UVM and building scalable, reusable testbenches
  • Comfortable working with standard IP interfaces and protocols such as PCIe, Ethernet, AXI/AMBA, or ARM/ARC CPUs
  • Thrives in a fast-paced startup environment and can take ownership of projects with minimal direction
  • Collaborates with cross-functional teams — RTL, software, emulation — and can clearly communicate technical insights.

Skills

Required:SystemVerilogUVMIP/SoC integrationPCIe
Nice to have:EthernetAXI/AMBA

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch + dinner in our office
  • Unlimited compute budget subject to ROI justification
Last updated Oct 15, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
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