ASIC Engineer, Design Verification
Meta· Hardware
BangaloreFull-timePosted 3mo ago
About the role
Meta is hiring an ASIC Design Verification Engineer to build IP and SoC for data center applications. The role covers verification planning, UVM-based testbench development, and verification closure using simulations, Formal, and Emulation, with collaboration across Design, Emulation, Silicon validation, and software teams to enable first-pass silicon success.
Responsibilities
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification criteria
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 2+ years of experience in SystemVerilog/UVM (Universal Verification Methodology) and/or C/C++ based verification
- Experience in System Verilog Assertions, Formal, Emulation (preferred if applicable)
- Experience in EDA/Electronic Design Automation tools and scripting (Python, TCL, Perl, Shell)
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Skills
Required:SystemVerilog/UVMC/C++
Nice to have:Formal / EmulationPython/Tcl/Perl/Shell scripting
Last updated Oct 23, 2026. Interested? Apply on the company site.
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