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ASIC DV Engineer, Simulation Acceleration and Hybrid Verification

Meta· Hardware
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BangaloreFull-timePosted 3mo ago

About the role

ASIC Verification Engineer focused on Simulation Acceleration using Emulation and Hybrid Platforms to develop IP/SoC for data center applications, with responsibilities spanning test-planning, hybrid test bench development, verification closure, and collaboration across full stack software, hardware, ASIC design, emulation, and post-silicon teams.

Responsibilities

  • Propose, implement and promote the Simulation Acceleration and Hybrid Verification Methodology to be used across the group, both at the Cluster and at the SoC level
  • Work with Architecture and Design teams to come up with functional, use case and performance test plan for the DUT
  • Define Verification scope, create environment, testplans and close use case scenarios and performance using targeted tests at Cluster and SoC level
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Develop and drive continuous Hybrid Verification improvements using the latest methodologies, tools and technologies from the industry
  • Build reusable/scalable environments for Hybrid Verification. Evaluate and recommend solutions for Hybrid Verification and Simulation Acceleration
  • Provide training for internal teams and mentoring of engineers related to Hybrid Verification Methodology

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of relevant experience
  • Hands-on experience in Verilog, SystemVerilog, UVM, C/C++, Python based verification
  • Experience of working with Zebu, Palladium, Veloce HW platforms
  • Experience in Cluster and SoC level verification using Hybrid Simulation and Emulation based methodologies
  • Proficiency in scripting languages such as Python, Perl, or TCL to build tools and flows for verification environments
  • Experience in architecting and implementing Hybrid Verification infrastructure and executing verification cycle

Skills

Required:VerilogSystemVerilogUVMC/C++PythonZebuPalladiumVeloceHybrid Verification
Last updated Oct 23, 2026. Interested? Apply on the company site.

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