ASIC Engineer, Design Verification
Meta· Hardware
Hybrid (Sunnyvale, CA)$178k - $250kFull-timePosted 3mo ago
About the role
Staff ASIC Design Verification Engineer at Meta, driving verification strategy and execution for custom silicon powering data center infrastructure. Lead end-to-end verification of IP blocks and SoCs for AI/ML acceleration, networking, and video processing workloads; architect UVM-based verification environments, define coverage models, and coordinate with design, emulation, and post-silicon validation teams to achieve first-pass silicon success.
Responsibilities
- Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring the highest design quality
- Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry
Qualifications
- Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
- 8+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
- 8+ years experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in one or more of the following areas along with functional verification-SV Assertions, Formal, Emulation
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
- Experience in architecting and implementing Design Verification infrastructure and executing the full verification cycle
Skills
Required:SystemVerilog/UVMC/C++IP/Sub-system/SoC verificationED A tools and scriptingUVM/OVM based methodologiesDebugging
Benefits
- Bonus
- Equity
- Benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.
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