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ASIC Engineer, Design Verification

Meta· Hardware
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Sunnyvale, CA$146k - $209kFull-timePosted 3mo ago

About the role

Meta is hiring an ASIC Design Verification Engineer to build IP and SoCs for data center applications. The role involves verification planning, UVM-based test bench development, and achieving verification closure using simulation, formal, and emulation, with collaboration across Design, Model, Emulation, Silicon validation, and Post-Silicon teams.

Responsibilities

  • Define and implement IP/SoC verification plans, build verification test benches to enable IP/sub-system/SoC level verification
  • Develop functional tests based on verification test plan
  • Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
  • Debug, root-cause and resolve functional failures in the design, partnering with the Design team
  • Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality meets defined verification and coverage goals
  • Develop and drive continuous Design Verification improvements using the latest verification methodologies, tools and technologies from the industry

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 6+ years of hands-on experience in SystemVerilog/UVM methodology and/or C/C++ based verification
  • 6+ years of experience in IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
  • Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments

Skills

Required:SystemVerilog/UVMC/C++IP/SoC verificationPython/Scripting
Last updated Oct 23, 2026. Interested? Apply on the company site.

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