ASIC Engineer, Design Verification
Meta· Engineering
Sunnyvale, CA$114k - $172kFull-timePosted 3mo ago
About the role
Meta is hiring an ASIC Design Verification Engineer to build IP and SoC for data center applications. The role focuses on verification closure from test planning to UVM-based bench development, with additional approaches like Formal and Emulation, collaborating with cross-functional teams to enable first-pass silicon success.
Responsibilities
- Define and implement block/IP/SoC verification plans, build verification test benches to enable block/IP/sub-system/SoC level verification
- Develop functional tests based on verification test plan
- Drive Design Verification to closure based on defined verification metrics on test plan, functional and code coverage
- Debug, root-cause and resolve functional failures in the design, partnering with the Design team
- Collaborate with cross-functional teams like Design, Model, Emulation and Silicon validation teams towards ensuring design quality through defined verification metrics and coverage goals
Qualifications
- Currently has, or is in the process of obtaining a Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience. Degree must be completed prior to joining Meta
- 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification
- 2+ years experience in block/IP/sub-system and/or SoC level verification based on SystemVerilog UVM/OVM based methodologies
- Experience in EDA tools and scripting (Python, TCL, Perl, Shell) used to build tools and flows for verification environments
Skills
Required:SystemVerilog/UVMC/C++Verification planning and test bench developmentPython, TCL, Perl, Shell scripting
Benefits
- benefits information referenced in the job description: not listed as explicit bullet items within the responsibilities/qualifications section; see overall posting for benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.
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