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Research Engineer, Chip Design RL (Reinforcement Learning)

Anthropic· AI Research & Engineering
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San Francisco, CA, New York City, NYFull-timePosted 3mo ago

About the role

Research Engineer role focusing on applying reinforcement learning to silicon design, including RTL generation, verification, and physical design optimization for ASIC/FPGA workloads, with production and research integration.

Responsibilities

  • Invent, design, and implement RL environments and evaluations for agentic RTL generation, design (including formal) verification, physical design optimization.
  • Work on cross-cutting RL considerations such as EDA-tool latency optimization and proxy rewards.
  • Conduct experiments and shape roadmap.
  • Deliver work into research and production training runs.
  • Collaborate with other researchers and engineers across and outside Anthropic.

Qualifications

  • Expertise in ASIC or FPGA design: RTL, design verification (UVM, formal methods, coverage-driven), physical design (synthesis, place-and-route, timing closure), PPA optimization, DFT, ECOs.
  • Fluent with industry EDA tools and processes.
  • Have taped out chips and experience going from spec to silicon.
  • Ability to balance research exploration with engineering implementation.
  • Passionate about AI's potential and committed to developing safe and beneficial systems.

Skills

Required:ASIC or FPGA designIndustry EDA toolsChip tape-out experienceBalancing research and engineering
Nice to have:Reinforcement learning experience

Benefits

  • Competitive compensation and benefits
  • Optional equity donation matching
  • Generous vacation and parental leave
  • Flexible working hours
  • Office space for collaboration
Last updated Jul 15, 2026. Interested? Apply on the company site.

About Anthropic

building reliable, interpretable, and steerable AI systems

Anthropic is an AI safety and research company that's working to build reliable, interpretable, and steerable AI systems.

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