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Design Verification Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Palo Alto, CA$135k - $155kfull-timePosted 3mo ago

About the role

Design Verification Engineer role at SpaceX for silicon/ASIC verification in the Starlink program, focusing on digital ASIC verification at block/system level, testbench development, pre/post-silicon validation, and automation in a fast-paced aerospace environment.

Responsibilities

  • Responsible for digital ASIC verification at block and system level
  • Write and review test plans, develop test harnesses and test sequences
  • Develop SystemVerilog testbench infrastructure (both UVM and non-UVM) for testing designs, including DSP blocks
  • Responsible for test plan execution, running regressions, code and functional coverage closure
  • Automate test case generation by using Python and MATLAB programs
  • Contribute towards pre-silicon verification, chip bring-up and post-silicon validation
  • Be a hands-on self-starter who can execute the steps required to fully verify a complex digital designs

Qualifications

  • Bachelor’s degree in electrical engineering, computer science or computer engineering
  • 1+ years of experience with design verification and test bench development

Skills

Required:Design verificationTest plan developmentSystemVerilog
Nice to have:PythonMATLAB

Benefits

  • comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • short & long-term disability insurance
  • life insurance
  • paid parental leave
  • 3 weeks of paid vacation & 10+ paid holidays per year
  • sick leave and other discounts and perks
  • long-term incentives such as stock options or cash awards
  • Employee Stock Purchase Plan
Last updated Jul 15, 2026. Interested? Apply on the company site.

About SpaceX

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