← All roles

Senior/Principal Physical Design Engineer

Fractile· Silicon
Apply on company site
Hybrid (London)Full-timePosted 3mo ago

About the role

Senior/Principal Physical Design Engineer at Fractile, London. Responsible for end-to-end implementation of complex IC physical designs from synthesis to sign-off, with potential full-chip ownership. Collaborates with cross-functional teams to optimise performance, power and area (PPA) while ensuring design integrity and manufacturability.

Responsibilities

  • Drive the physical implementation of ASIC/SoC designs, including floorplanning, placement, clock tree synthesis (CTS), routing, and sign-off, with potential responsibility for full-chip execution.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve the best PPA metrics.
  • Perform power planning and analysis, addressing IR drop, electromigration, and low-power design techniques.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design-for-test (DFT) structures into the physical implementation.
  • Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Interface with foundries and process engineers to ensure manufacturability and yield optimisation.
  • Work closely with RTL and architecture teams to drive design feasibility, constraints, and physical-aware RTL design.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.

Qualifications

  • Bachelor’ Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
  • 8+ years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below).
  • Strong proficiency in EDA tools for place & route, STA, and sign-off.
  • Solid understanding of CMOS technology, semiconductor physics, and process limitations.
  • Experience with low-power design methodologies, power optimisation techniques, and multi-power domain architectures.
  • Expertise in timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation.
  • Excellent problem-solving skills, communication, and teamwork in a collaborative design environment.
  • Experience in high-performance computing (HPC), AI accelerators, or networking chips.

Skills

Required:Physical design executionScripting for automationTiming analysis and STAPower integrity & low power designCMOS & semiconductor physics
Nice to have:DFT integration

Benefits

  • Competitive salary: A competitive salary reflective of your experience and the specialist nature of the role
  • Equity & Ownership: meaningful equity so everyone shares in the value creation.
  • Benefits: Private Medical, Dental and Vision, Contributory Pension, 25 Days holiday plus bank holidays and Life/Critical Illness Insurance.
Last updated Aug 20, 2026. Interested? Apply on the company site.
Fractile logo

About Fractile

Radically Accelerate Frontier Model Inference

Fractile is designing AI compute systems that will enable the next generation of AI scaling: frontier model inference, 25x faster, at 1/10th the cost.

frontier model inferenceAI computecompute systemsAI scalinginference hardwareprocessor innovation
Company profileWebsite

More open roles at Fractile