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Principal DFT Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Hybrid (Austin, TX)full-timePosted 2mo ago

About the role

Principal DFT Engineer role focused on developing and optimizing Design for Test (DFT) architectures for ASICs in SpaceX Starlink projects, leading DFT implementation, ATPG, scan insertion, and verification efforts across RTL to gate-level, with a strong emphasis on test methodologies, automation, and cross-functional collaboration.

Responsibilities

  • Lead implementation and optimization of DFT architectures, including scan insertion, compression/decompression logic, memory BIST, and logic BIST, leveraging Siemens Tessent tools for RTL and gate netlist DFT implementation
  • Own ATPG tools and methodologies, including generating patterns for stuck-at, transition, and path delay fault models, with focus on pattern compression, diagnosis, and hierarchical test flows. Provide post-silicon testing and validation support
  • Evaluate design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integrate and verify Design for Test (DFT) fabrics and IP within Subsystems
  • Run and debug non-timing and SDF annotated gate level simulations
  • Develop test scripts, automate processes, and analyze data using Perl, Python, Tcl, or C++

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 10+ years of experience working with ASICs
  • 10+ years of experience in scan insertion and DFT setup, integration and validation

Skills

Required:DFT architecture developmentATPGRTL/Physical design for DFTDFT integrationGate-level simulationProgramming for automation
Nice to have:Leadership in SOC DFT execution
Last updated Aug 5, 2026. Interested? Apply on the company site.

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