← All roles

Power Integrity Engineer

Etched· Platform
Apply on company site
San JoseFull-timePosted 2mo ago

About the role

Power Integrity (PI) Engineer responsible for the PI methodology for high-power PCB and system designs, from architecture to final release, ensuring robust power delivery to high-performance ASICs and support components across operating conditions.

Responsibilities

  • Perform pre- and post-layout PDN analysis for high-current ASIC power rails: target impedance profiling, decoupling capacitor selection and placement optimization, and plane resonance analysis.
  • Execute DC IR-drop and current density simulations; define copper weight, plane shapes, via stitching, and layer allocation requirements for PCB designers.
  • Conduct AC impedance analysis from VRM output through package and die, including ESR/ESL modeling of the full decoupling network.
  • Develop and validate VRM models; analyze load transient response, AVP/load-line behavior, and multiphase converter performance against ASIC power specifications.
  • Perform power-plane thermal co-simulation and work with mechanical teams on thermal-electrical tradeoffs for high-current delivery.
  • Drive design rule checks for PI compliance; work with layout teams in Cadence Allegro / Sigrity PowerDC/PowerSI or Ansys SIwave.
  • Collaborate with power design, PCB layout, and ASIC/package teams to define power delivery architecture and review guidelines early in the product lifecycle.
  • Support bring-up, debug rail-level issues (droop, ripple, transient excursions), and document root-cause findings with clear corrective actions.
  • Develop and maintain simulation-to-hardware correlation databases to continuously improve PDN modeling accuracy.

Qualifications

  • B.S. or M.S. in Electrical Engineering or a closely related discipline.
  • 5+ years of hands-on PI experience on high-current, high-performance designs (ASIC/CPU/GPU power delivery, server boards, or accelerator platforms).
  • Proficiency with industry PI EDA tools (Ansys SIwave, Cadence Sigrity PowerDC/PowerSI/OptimizePI, or equivalent).
  • Strong understanding of target impedance methodology, decoupling network design, plane resonances, and anti-resonance mitigation.
  • Experience with DC IR-drop analysis, current density limits, and via/plane current-carrying capacity.
  • Working knowledge of VRM fundamentals: buck converter operation, multiphase design, transient response, and load-line/AVP concepts.
  • Working knowledge of multi-layer PCB stack-up design and power plane allocation strategies.

Skills

Required:Power integrity methodologyPDN analysisDC IR-drop analysisAC impedance analysisVRM modelingThermal co-simulationPI toolchain

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2,500 per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch and dinner in our office
  • Unlimited compute budget subject to ROI justification
Last updated Sep 17, 2026. Interested? Apply on the company site.
Etched logo

About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
Company profileWebsite

More open roles at Etched