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RTL Design Lead/IC Front-End Architect/Datapath Lead

Lumilens· Engineering
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San JoseFull-timePosted 2mo ago

About the role

Lead role owning end-to-end verification and front-end architecture for a first-of-its-kind chiplet, defining methodology, micro-architecture, and high-speed datapath interfacing (UCIe) with optical front end. Founding hire responsible for partitioning, interfaces, coding/CDC standards, and mentoring the front-end team.

Responsibilities

  • Front-end micro-architecture and block partitioning; the architecture spec the RTL team builds to.
  • Front-end design methodology and quality: RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy across the team.
  • The high-speed datapath: per-lane alignment/deskew/mux, the UCIe streaming /RDI adapter, elastic FIFOs, and custom logic.
  • Transport/link framing/mapping and the adaptation logic.
  • Timing- and floorplan-aware micro-architecture: pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps.
  • Clocking, reset, and low-power architecture — clock/reset domains, gating strategy, and UPF power intent.
  • Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA) coverage.
  • Architectural DFT and debug provisioning — scan-friendly structure and on-die observability/controllability.
  • IP integration and interface/register conventions; parameterization for configurability across lane counts/configurations.
  • Architectural trade-offs with modelling lead and DV lead.
  • Lead, grow, and mentor the front-end design team as the group scales.

Qualifications

  • 10+ years digital design / micro-architecture with lead ownership of a high-throughput datapath or SerDes-adjacent SoC
  • Experience designing the datapath of a network switch/NIC or memory controller at a major XPU / fabric vendor (or comparable high-throughput datapath)
  • Solid understanding of scale-up vs. scale-out interconnect architectures and bandwidth/latency trade-offs
  • Strong SystemVerilog RTL and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; CDC discipline
  • Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew
  • Ownership of front-end design methodology — lint/CDC/RDC signoff, clocking/reset architecture, and design-for-test/physical-closure collaboration
  • Track record translating system requirements into an implementable, verifiable architecture spec

Skills

Required:Front-end micro-architectureRTL design methodologyUCIe/PCIe/CXL datapath conceptsSystemVerilogVerification planning and DFT/diagnosticsIP integration

Benefits

  • Competitive salary commensurate with experience
  • Comprehensive benefits package including health, dental, and vision
  • Professional development opportunities and certification support
  • Access to cutting-edge technology and cloud platforms
  • Collaborative work environment with cross-functional teams
Last updated Aug 8, 2026. Interested? Apply on the company site.

About Lumilens

Connectivity Platform for AI

Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.

Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
Company profileWebsite

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