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RTL Design Lead/IC Front-End Architect/Datapath Lead

Lumilens· Engineering
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Bengaluru, IndiaFull-timePosted 2mo ago

About the role

Lead role owning end-to-end verification and front-end micro-architecture for a first-of-its-kind chiplet, defining methodology before RTL, and driving high-speed datapath, interfaces, and DFT/verification across a growing front-end design team.

Responsibilities

  • Front-end micro-architecture and block partitioning; the architecture spec the RTL team builds to.
  • Front-end design methodology and quality: RTL coding standards, lint, CDC/RDC signoff, and clean-RTL policy across the team.
  • The high-speed datapath: per-lane alignment/deskew/mux, the UCIe streaming /RDI adapter, elastic FIFOs, and custom logic.
  • Transport/link framing/mapping and the adaptation logic.
  • Timing- and floorplan-aware micro-architecture: pipelining, retiming, and partitioning for physical closure at multi-hundred-Gbps (with the backend team).
  • Clocking, reset, and low-power architecture — clock/reset domains, gating strategy, and UPF power intent.
  • Establish designer-level verification: block-level testbenches/sanity checks and assertion (SVA) coverage that designers own before handoff to DV.
  • Architectural DFT and debug provisioning — scan-friendly structure and on-die observability/controllability for a die you can't probe (with the DFT and DV leads).
  • IP integration and interface/register conventions; parameterization for configurability across lane counts/configurations.
  • Architectural trade-offs with the modelling lead (latency, buffering, datapath sampling/observability) and the DV lead (verifiability and debug).
  • Lead, grow, and mentor the front-end design team as the group scales (datapath, interfaces, integration).

Qualifications

  • 10+ years digital design / micro-architecture, with lead ownership of a high-throughput datapath or SerDes-adjacent SoC.
  • Experience designing the datapath of a network switch/NIC card or memory controller at a major XPU / fabric vendor (or a comparable high-throughput, high-reliability datapath).
  • Solid understanding of scale-up vs. scale-out interconnect architectures and their bandwidth/latency trade-offs.
  • Strong SystemVerilog RTL and timing-aware micro-architecture at multi-hundred-Gbps aggregate rates; CDC discipline.
  • Working command of UCIe/PCIe/CXL datapath concepts and high-speed lane alignment/deskew.
  • Proven ownership of front-end design methodology — lint/CDC/RDC signoff, clocking/reset architecture, and design-for-test and physical-closure collaboration.
  • Track record translating system requirements into an implementable, verifiable architecture spec.

Skills

Required:Front-end micro-architectureHigh-speed datapath designUCIe/PCIe/CXL datapath conceptsSystemVerilog RTLVerification planning

Benefits

  • Competitive salary commensurate with experience
  • Comprehensive benefits package including health, dental, and vision
  • Professional development opportunities and certification support
  • Access to cutting-edge technology and cloud platforms
  • Collaborative work environment with cross-functional teams
Last updated Aug 8, 2026. Interested? Apply on the company site.

About Lumilens

Connectivity Platform for AI

Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.

Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
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