IC/RTL Design Engineer
Lumilens· Engineering
San JoseFull-timePosted 2mo ago
About the role
You design and implement the digital front-end RTL at the heart of the chip, including the high-speed datapath between UCIe and the optical front end. The role involves micro-architecture to RTL implementation, block-level verification, and collaboration across architecture, DV, DFT, and backend teams with room to grow as the chip matures.
Responsibilities
- Develop block-level micro-architecture for assigned blocks, and contribute to interface and register definitions.
- Design and implement front-end RTL blocks in SystemVerilog — datapath elements, the UCIe streaming/RDI adapter, elastic FIFOs, and supporting logic.
- Integrate IP and support parameterization for configurability.
- Write clean, lint-clean, CDC/RDC-clean RTL that follows coding and quality standards.
- Write block-level testbenches, sanity checks, and assertions (SVA) for your own blocks before handoff to DV.
- Power- and timing-aware design — managing block activity, clock-gating, pipelining, and retiming; coordinate with backend for physical closure.
- Bring-up and debug across simulation and emulation / FPGA prototyping; support DV and silicon bring-up, including DFT/debug hooks in your blocks.
- Collaborate with architecture, modelling, DV, DFT, and backend teams as blocks move through the flow.
Qualifications
- BS or MS in Electrical/Computer Engineering (or equivalent experience).
- 3+ years of digital RTL design in SystemVerilog, with blocks taken from micro-architecture through to verification handoff.
- Solid digital design fundamentals: pipelining, FSMs, FIFOs, clock-domain crossing, and streaming/bus interfaces (e.g., AXI).
- Lint and CDC/RDC discipline and clean-RTL practices.
- Power- and timing-aware design practices; comfortable with synthesis and timing closure, working with the backend team.
- Strong debug skills in simulation; scripting in Python, Perl, or TCL.
Skills
Required:SystemVerilogMicro-architecture to RTL flowCDC/CAD lintingPython, Perl, or TCL scripting
Last updated Sep 5, 2026. Interested? Apply on the company site.
About Lumilens
Connectivity Platform for AI
Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.
Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
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