Senior/Staff Process Engineer (Wafer Dicing & Back-grind)
Lumilens· Operations
SingaporeFull-timePosted 2mo ago
About the role
Senior/Staff level process engineering role focused on silicon photonic wafer backside grinding/thinning, laser stealth dicing, and die sorting development for silicon photonic chips, with emphasis on process optimization, yield improvement, and NPI support.
Responsibilities
- Responsible for silicon photonic wafer backside grinding/thinning process, laser stealth dicing process and die sorting development for silicon photonic chips, with OSAT or internal line.
- Optimize wafer thinning thickness, grinding speed, cutting path and laser cutting parameters to avoid chip crack, edge chipping and optical structure damage of silicon photonic wafers.
- Solve process abnormalities in wafer thinning and dicing processes, including wafer warpage, surface scratch, incomplete cutting and chip breakage.
- Monitor wafer thickness uniformity, cutting quality and production capacity, carry out continuous process optimization to improve product yield.
- Evaluate process compatibility between wafer grinding/stealth dicing and bumping & flip-chip processes, optimize process integration to avoid subsequent process failure attributed to front-end process variations.
- Compile process SOP, WI, failure reports and engineering change documents; support NPI new product introduction and process verification.
Qualifications
- A Bachelor or Master degree in Materials Science, Chemical Engineering, Mechanical Engineering, Microelectronics, or an equivalent technical discipline.
- 3 to 6+ years of hands-on process engineering in wafer mounting, stealth dicing, wafer grinding, especially in handling advanced packaging wafers with more complex topology or stack.
- Experience working with external equipment and material suppliers to develop equipment and materials needed to support new assembly requirements. Characterize, qualify and bring the process up for mass production.
- Familiarity with SPC, JMP data analysis, and DOE matrix design for process development and problem identification and solving using meticulous fixing methods.
Skills
Required:Wafer mountingStealth dicingWafer grindingProcess optimization
Nice to have:NPI support
Last updated Oct 17, 2026. Interested? Apply on the company site.
About Lumilens
Connectivity Platform for AI
Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.
Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
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