Design Verification Engineer, Hardware
Hybrid (Austin, TX and Palo Alto, CA)$200k - $420kFull-timePosted 2mo ago
About the role
Design verification engineer role focused on ensuring high-performance custom silicon is functionally correct, collaborating across RTL design, performance modeling, verification, and compiler teams.
Responsibilities
- Verification Strategy & Planning: Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks.
- UVM Environment Development: Architect and implement scalable, reusable, and robust test benches using SystemVerilog and UVM.
- Constrained-Random Testing: Develop complex sequences and test cases to achieve high functional coverage, ensuring the design handles architectural corner cases and error conditions.
- Coverage-Driven Verification: Define and implement functional coverage models and perform detailed code coverage analysis to quantify verification progress.
- Formal Verification: Leverage formal methods (SVA, Property Checking) where applicable to exhaustively prove the correctness of critical logic.
- Emulation: Use emulation and prototyping platforms like ZeBu/HAPS and Palladium/Protium to perform scaled testing.
- Debug & Analysis: Debug failures using waveform viewers and work closely with RTL designers to resolve functional bugs and architectural non-compliance.
- Automation & Scripting: Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL to streamline the verification cycle.
Qualifications
- Bachelor’s degree in Electrical Engineering or Computer Engineering or Computer Science, and 5+ years industry experience.
- Deep, hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors).
- Expert command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage.
- Strong understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI).
- Proven track record of verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
- A highly collaborative mindset and a bias for action to push boundaries and co-design effectively with other engineers.
Skills
Required:UVM-based verification environmentsSystemVerilogComputer architecture
Benefits
- generous health, dental, and vision benefits
- unlimited PTO
- relocation support as needed
Last updated Sep 23, 2026. Interested? Apply on the company site.
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