Physical Design Engineer, Hardware
Hybrid (Austin, TX), Hybrid (Palo Alto, CA)$200k - $420kFull-timePosted 2mo ago
About the role
Physical Design Engineer role focused on transforming high-performance architectural concepts into production-ready silicon, owning the physical implementation flow from synthesis to tape-out, and collaborating with RTL design to meet timing, electrical, and physical verification targets for a custom AI accelerator.
Responsibilities
- Drive Synthesis and Place-and-Route: Own the physical implementation flow from RTL synthesis through placement, clock tree synthesis (CTS), and routing for high-performance blocks.
- Maximize PPA: Optimize layout topologies to maximize cell density and utilization, architect robust PDN to minimize IR drop and meet aggressive frequency targets on advanced foundry nodes.
- Close Timing & Electricals: Conduct static timing analysis (STA), fix setup/hold violations across complex clock domains, and resolve signal integrity (SI), electromigration (EM) and IR-drop constraints.
- Execute Physical Verification: Run and debug sign-off physical verification, including DRC, LVS, and Antenna rule compliance.
- Co-Design with RTL: Partner with RTL team to provide early physical feedback on logic structures, pipeline depth, and routing congestion to streamline implementation closure.
- Advance Flow Automation: Integrate and develop AI-driven EDA tools and workflows to accelerate physical implementation and design closure.
Qualifications
- Bachelor’s degree in Electrical Engineering or Computer Engineering
- 5+ years practical industry experience with advanced process nodes (7nm or below)
- Deep hands-on proficiency with industry-standard physical design, timing, and sign-off tools (e.g., Innovus, Fusion Compiler, PrimeTime, RedHawk)
- Proven track record running logic synthesis, integrating compiled memory macros, and managing multi-voltage design techniques using UPF/CPF
- Exceptional debugging skills with first-principles approach to congestion, timing slack, and power density in highly utilized designs
- Collaborative mindset and bias for action to co-design effectively with RTL and architecture teams
Skills
Required:RTL-to-physical flowStatic Timing Analysis (STA)Signal Integrity, EM, IR-dropPhysical Verification (DRC/LVS/Antenna)PDN and power/ground designSynthesis/Place-and-Route tools
Benefits
- generous health, dental, and vision benefits
- unlimited PTO
- relocation support as needed
Last updated Sep 23, 2026. Interested? Apply on the company site.
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