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ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Hybrid (Austin, TX)Full-timePosted 2mo ago

About the role

ASIC/SOC DFT Engineer role at SpaceX, focusing on Design for Test (DFT), scan insertion, ATPG, and integration with RTL/physical design to enable high-quality silicon for Starlink hardware.

Responsibilities

  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
  • Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
  • Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
  • Run and debug non-timing and SDF annotated gate level simulations
  • Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
  • Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 1+ years of professional experience working with ASICs
  • Experience in scan insertion or DFT setup

Skills

Required:Design for Test (DFT)
Nice to have:Verilog/SystemVerilogScriptingUPFDFT tooling
Last updated Aug 12, 2026. Interested? Apply on the company site.

About SpaceX

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