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ASIC/SOC DFT Engineer (Silicon Engineering)

SpaceX· Silicon Engineering
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Palo Alto, CA$135k - $210kPosted 2mo ago

About the role

Electrical engineer role focused on Design for Test (DFT) and scan insertion for next-generation ASICs/SOCs used in SpaceX Starlink infrastructure, involving RTL/physical design, ATPG, and collaboration with cross-functional teams.

Responsibilities

  • Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools
  • Integration and verification of Design for Test (DFT) fabrics and IP within Subsystems
  • Running and evaluating scan insertion through synthesis tools and refining scan insertion recipe for maximum coverage
  • Run ATPG(Automatic Test Pattern Generation) analysis to ensure quality scan chain construction and meeting basic coverage goals
  • Run and debug non-timing and SDF annotated gate level simulations
  • Creating ATPG content for use in post-silicon testing and validating that content through gate level simulation
  • Collaborate with circuit physical design team, ATPG team and manufacturing team to facilitate high quality scan coverage in silicon

Qualifications

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 1+ years of professional experience working with ASICs
  • Experience in scan insertion or DFT setup

Skills

Required:ASIC/DFT concepts and scan insertion
Nice to have:Verilog/SystemVerilogScripting

Benefits

  • Base salary and bonus potential disclosed (compensation range provided)
  • Long-term incentives (stock or long-term cash rewards)
  • Comprehensive medical, vision, and dental coverage
  • 401(k) retirement plan
  • Short and long-term disability insurance
  • Life insurance
  • Paid parental leave
  • Paid vacation and holidays
  • Employee stock purchase plan (ESPP)
  • Various discounts and other perks
Last updated Aug 12, 2026. Interested? Apply on the company site.

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