← All roles

Senior Hardware Design Engineer

SambaNova· Hardware
Apply on company site
Hybrid (San Jose, CA), Hybrid (Austin, TX)$120k - $200kfull-timePosted 2mo ago

About the role

Senior Hardware Design Engineer to design RTL blocks for SambaNova's Reconfigurable Dataflow Unit (RDU) ASICs, collaborating with principal engineers, architects, and cross-functional teams. Onsite role based in San Jose, CA or Austin, TX.

Responsibilities

  • Work with principal engineers and architects to author sections of the microarchitecture specification for compute, memory, or networking subsystems.
  • Code, integrate, and debug SystemVerilog RTL for assigned blocks through the chip implementation and production lifecycle.
  • Meet Power, Performance, and Area (PPA) targets for your blocks using advanced digital design techniques for high-speed design.
  • Partner with design verification and physical design engineers to converge on functionality, timing, and area.
  • Implement SystemVerilog Assertions (SVA) and run lint, CDC, and LEC flows to check design intent and keep blocks clean.
  • Participate in design reviews, presenting your design decisions and incorporating feedback.
  • Support post-silicon bring-up and debug for the blocks you own.
  • Contribute to design flow improvements, including AI and automation in EDA tool methodologies.

Qualifications

  • Master's degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or Bachelor's degree with 5–7 years.
  • Solid foundation in computer architecture and digital logic design.
  • Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
  • Experience making design decisions that trade off Power, Performance, and Area (PPA).
  • Working knowledge of industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
  • Experience with digital logic synthesis tools and Static Timing Analysis (STA).
  • Proficiency with industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).
  • Experience implementing SystemVerilog Assertions (SVA) to check design intent.
  • Familiarity with tools and simulators for hardware performance analysis and tuning.
  • Familiarity with Git for managing release cycles.
  • Scripting skills in Python and Linux shell.
  • Ability to work onsite in San Jose, CA or Austin, TX.

Skills

Required:SystemVerilog RTL designPower/Performance/Area (PPA) optimizationSystemVerilog Assertions (SVA)EDA tools (lint, CDC, LEC, STA)Python and Linux shell scriptingGit

Benefits

  • Competitive total rewards package including base salary and equity.
  • Health Insurance premium coverage: 95% for employee, 77% for dependents.
  • Health Savings Account (HSA) with employer contribution.
  • Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance.
  • Flexible Spending Accounts (FSA) options (Health Care, Limited Purpose, Dependent Care).
  • Headspace subscription, Gympass+ membership, One Medical membership, Employee Assistance Program, and other well-being benefits.
Last updated Sep 13, 2026. Interested? Apply on the company site.

About SambaNova

The Fastest AI Inference Platform

Discover SambaNova - the complete AI platform delivering the fastest AI inference, fine-tuning, and scalable solutions for agentic AI easily integrated into existing data center infrastructures.

DataflowOpenAI gpt-oss-120bRDUSambaCloudSambaManagedSambaRackSambaStackSovereign AI
Company profileWebsite

More open roles at SambaNova