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Director of ASIC Design Verification

SambaNova· Hardware
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San Jose, CA$270k - $340kfull-timePosted 2mo ago

About the role

Director-level leadership role responsible for end-to-end ASIC design verification for SambaNova’s next-generation RDU chips, spanning pre-silicon verification through tape-out and into first silicon, with ownership of methodology, architecture, and team growth.

Responsibilities

  • Own verification through tape-out
  • Define verification architecture, strategy, schedules, and DV environments for complex, high-performance machine learning ASICs
  • Serve as the technical authority on verification: arbitrate testbench architecture, set coverage and sign-off criteria, and lead debug on the hardest failures
  • Set and defend the DV schedule and own tape-out readiness sign-off, including trade-offs between coverage depth and time to silicon; report risk and readiness to executive staff
  • Carry ownership into first silicon — support lab functional validation and bring-up debug, feeding findings back into the pre-silicon environment
  • Lead and grow the team: shape methodology, evolve or replace verification environment, coach principal engineers, and drive multi-workstream organization growth
  • Own the DV methodology end to end — verification architecture, reuse strategy, sign-off criteria
  • Lead development of test benches, agents, checkers, and stimulus at block, full-chip, system, and gate level
  • Drive pre-silicon debug and closure in functionality and performance; own regression health and root-cause discipline
  • Land new DV methodologies and processes, including AI-assisted verification workflows
  • Direct emulation and FPGA prototyping strategy; manage third-party verification IP evaluation and EDA vendor relationships for DV tooling
  • Partner across the organization to settle requirements and drive DV planning; map ML application flows into verification; validate silicon with lab validation and cross-functional reviews

Qualifications

  • BS in EE, CS, or CE with 12+ years of industry experience in ASIC design verification
  • 5+ years managing design verification engineers, including hiring and performance management
  • Track record of inheriting and evolving an established verification environment
  • Deep, current technical expertise in verification (methodology, testbench arbitration, debugging hard pre-silicon failures)
  • Full-cycle DV from planning through tape-out and into production silicon on at least one complex ASIC or large subsystem
  • Hands-on foundation in SystemVerilog, SVA, Python; knowledge of UVM/OVM/VMM
  • Experience through silicon bring-up, including lab functional validation and first-silicon debugging
  • Working knowledge of ML SoCs or microprocessors and modern computer architecture
  • Excellent communication and stakeholder consensus-building skills

Skills

Required:Verification architectureTest bench developmentDebug and root cause analysisDV methodologyLeadership and people management

Benefits

  • Competitive total rewards package including base salary and equity
  • Health insurance with partial premiums covered for employees and dependents; HSA employer contribution
  • Dental, Vision, Short/Long-term Disability, Basic/Voluntary Life, AD&D
  • Flexible Spending Accounts (FSA)
  • Well-being benefits including Headspace, Gympass+, One Medical, EAP, and more
Last updated Sep 13, 2026. Interested? Apply on the company site.

About SambaNova

The Fastest AI Inference Platform

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