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Principal RTL Design Engineer

SambaNova· Hardware
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Hybrid (Austin, TX / San Jose, CA)$180k - $255kfull-timePosted 2mo ago

About the role

Senior individual contributor role responsible for owning microarchitecture and RTL for major blocks/subsystems of SambaNova’s Reconfigurable Dataflow Unit (RDU), from specification through tape-out, with emphasis on power, performance, and area trade-offs and aggressive frequency targets.

Responsibilities

  • Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute, memory, or on-chip network subsystems
  • Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
  • Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
  • Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
  • Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures
  • Work with architects and software teams to prototype and evaluate features that improve application-level performance
  • Drive AI, automation, and new EDA tool methodologies into the design flow
  • Set the technical bar in design reviews and mentor design engineers

Qualifications

  • B.S. in Electrical Engineering, Computer Engineering, or Computer Science
  • 7+ years of industry experience in ASIC RTL design
  • Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
  • High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency targets
  • Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures
  • Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
  • Experience converging power, performance, and area against real physical constraints, including floorplan, congestion, and timing feedback from the physical design team
  • Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
  • Demonstrated technical leadership without formal authority, including setting direction in design reviews, arbitrating microarchitecture decisions, and mentoring engineers
  • Scripting in Python for design and flow automation

Skills

Required:SystemVerilogHardware designPython scripting

Benefits

  • Base salary plus equity and benefits
  • Health insurance with substantial employer premium coverage (medical, dental, vision)
  • Health Savings Account (HSA) with employer contribution
  • Flexible Spending Accounts (FSA) options
  • Headspace subscription
  • Gympass+ membership
  • One Medical membership
  • Employee Assistance Program and counseling services
Last updated Sep 13, 2026. Interested? Apply on the company site.

About SambaNova

The Fastest AI Inference Platform

Discover SambaNova - the complete AI platform delivering the fastest AI inference, fine-tuning, and scalable solutions for agentic AI easily integrated into existing data center infrastructures.

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