FPGA Verification Engineer, Air Dominance and Strike
Anduril· Air Dominance & Strike : Air Dominance & Strike Hardware : Digital Design
Costa Mesa, CA$146k - $194kFull-timePosted 2mo ago
About the role
Anduril Industries is hiring an FPGA Verification Engineer in Costa Mesa, CA to own verification of FPGA/SoC designs on AMD (Xilinx) platforms for flight-critical avionics, focusing on UVM-based verification, coverage-driven methodologies, and DO-254/safety standards.
Responsibilities
- Architect and implement UVM verification environments (drivers, monitors, predictors, scoreboards) for AMD (Xilinx) FPGA/SoC designs
- Develop verification plans with traceability to system and hardware requirements
- Author SystemVerilog Assertions (SVA) for protocol compliance and design intent checks
- Build functional coverage models and drive code coverage analysis to closure
- Develop constrained-random and transaction-level test sequences to maximize coverage and uncover corner-case bugs
- Establish and maintain regression suites, tracking coverage metrics and verification progress
- Debug failures using waveform tools and simulation logs at the HDL and system level
- Collaborate with design engineers on RTL reviews, bug resolution, and micro-architecture refinement
- Support hardware validation and board bring-up on target platforms
- Ensure verification meets DO-254 and relevant safety standards
- Author verification closure reports and coverage analysis summaries
Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field
- 2+ years of experience in FPGA/ASIC verification
- Proficient in SystemVerilog, UVM methodology and SVA, with experience contributing to and extending UVM testbenches
- Object-oriented programming principles
- Industry simulators (Questa, VCS, Xcelium, or Vivado)
- Git-based collaborative workflows including code review
- Linux development environments
- Strong communication and teamwork skills
- Eligible to obtain and hold a U.S. Secret security clearance
Skills
Required:SystemVerilogUVMSystemVerilog Assertions (SVA)Object-oriented programming
Last updated Aug 26, 2026. Interested? Apply on the company site.
About Anduril
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