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Analog Layout Lead, Silicon Engineering

Meta· Engineering
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Hybrid (Sunnyvale, CA)$178k - $250k + bonusFull-timePosted 1mo ago

About the role

Lead full-custom layout of analog and mixed-signal blocks for custom silicon in Meta's Silicon Engineering organization. Define methodologies, collaborate with circuit design and verification, and drive physical design from concept to tape-out with focus on power, performance, and area targets for VR/AR hardware.

Responsibilities

  • Lead full-custom layout of complex analog and mixed-signal blocks including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon targeting VR and AR wearable platforms
  • Define and enforce analog layout methodologies, design rules, and best practices across the physical design team
  • Drive parasitic-aware layout strategies to meet stringent noise, matching, and signal integrity requirements for mixed-signal designs
  • Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results
  • Own physical verification closure including DRC, LVS, and antenna checks across advanced process nodes
  • Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts
  • Provide technical guidance and layout direction to other engineers on the team, reviewing layouts and driving consistency in methodology
  • Partner with process technology and design kit teams to evaluate new process nodes and contribute to PDK qualification for analog layout
  • Identify and resolve layout-induced performance issues through post-layout simulation analysis and iterative design refinement
  • Own long-term physical design roadmaps and methodology investments that scale across multiple silicon programs
  • Manage layout contractors to deliver high-quality final GDS on schedule and in alignment with design specifications

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes (28nm or below)
  • 8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification
  • Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out
  • Experience defining and implementing layout methodologies for matching, shielding, and noise isolation in mixed-signal environments
  • Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints and implementation decisions
  • Experience managing and mentoring layout engineers and coordinating work with external contractors

Skills

Required:Analog full-custom layoutLayout methodologiesParasitic extraction and LVS/DRCCollaboration with circuit designers
Last updated Oct 23, 2026. Interested? Apply on the company site.

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