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Advanced Packaging SI/PI Engineer

Etched· Architecture
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San Jose$150k - $400kFull-timePosted 1mo ago

About the role

Signal & Power Integrity Engineer focusing on electrical performance of an AI accelerator platform across silicon, package, and board, with emphasis on high-power packaging, PDN design, and high-speed signaling in 2.5D/3D packaging.

Responsibilities

  • SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
  • Interact with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize electrical performance
  • Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out
  • Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails
  • Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams
  • Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization
  • Participating in cross-functional meetings and design reviews

Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals
  • 8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms
  • Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis
  • Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces
  • Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS
  • Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs
  • Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization
  • Strong analytical and communication skills, comfortable presenting risk, sign-off status, and trade-offs to cross-functional leadership
  • Deeply creative and able to think from first principles

Skills

Required:Signal integrity (SI)Power integrity (PI)High-speed interfacesCoWoS / advanced packaging

Benefits

  • Medical, dental, and vision packages with generous premium coverage
  • $500 per month credit for waiving medical benefits
  • Housing subsidy of $2.5k per month for those living within walking distance of the office
  • Relocation support for those moving to San Jose (Santana Row)
  • Various wellness benefits covering fitness, mental health, and more
  • Daily lunch and dinner in our office
  • Unlimited compute budget subject to ROI justification
Last updated Oct 15, 2026. Interested? Apply on the company site.
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About Etched

Etched is building frontier inference clusters: co-designs chips, racks, software and manufacturing to push the pareto frontier for AI hardware.

frontier inference clustersAI hardwarechipsrackssoftwaremanufacturingparto frontier
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