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SOC Architect, Reality Labs Silicon

Meta· Hardware
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Sunnyvale, CA$178k - $250kFull-timePosted 1mo ago

About the role

SoC Architect responsible for driving top-level architecture for AR/AI wearable chips, focusing on power, size, and integration across heterogeneous compute blocks within Reality Labs Silicon.

Responsibilities

  • Define and drive SoC-level architecture for AR or AI wearable chips, including compute subsystems, memory hierarchy, interconnect topology, and power delivery strategies
  • Lead architectural exploration and trade-off analysis across heterogeneous compute blocks, including CPU, GPU, vision, audio, and ML accelerators
  • Collaborate with algorithms, firmware, and software teams to drive hardware-software co-design decisions
  • Partner with IP vendors, power and performance architects, IP architects, and internal design teams to evaluate and integrate third-party and custom IP blocks into the SoC architecture
  • Develop architectural specifications, interface definitions, and design guidelines that guide RTL implementation and physical design teams
  • Provide architectural leadership and technical direction to other engineers across silicon, systems, and platform teams working on wearable device programs
  • Contribute to long-term silicon roadmap planning by evaluating emerging process technologies, memory technologies, and compute paradigms relevant to AR/VR applications

Qualifications

  • Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
  • 8+ years of experience in SoC architecture, microarchitecture definition, or system-level hardware design for consumer electronics or mobile/wearable platforms
  • Experience architecting heterogeneous SoCs, encompassing CPU, GPU, neural processing, and hardware accelerator subsystems
  • Expertise with high-speed I/O interfaces such as PCIe, USB, and LPDDR
  • Experience with memory subsystem architecture, including cache hierarchy design, DRAM interface optimization, and on-chip interconnect (NoC) design
  • Experience collaborating across hardware, firmware, and software disciplines to drive hardware-software co-design for real-time or latency-constrained workloads

Skills

Required:SoC architecture and microarchitectureCPU, GPU, neural processing, and hardware accelerator subsystemsHigh-speed I/O interfaces (PCIe, USB, LPDDR)

Benefits

  • Benefits information provided in the posting (explicit benefits not enumerated in text)
  • Equity and bonus (as part of compensation)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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