Analog Layout Lead
Lumilens· Engineering
San JoseFull-timePosted 1mo ago
About the role
We are seeking an Analog Layout Lead to drive full-custom analog and mixed-signal layout for Lumilens’ next-generation silicon platforms, lead complex physical implementation across advanced CMOS nodes, and establish layout methodologies to ensure performance, reliability, manufacturability, and tape-out readiness.
Responsibilities
- Lead full-custom layout of complex analog and mixed-signal blocks, including PLLs, ADCs, DACs, LDOs, bandgaps, and high-speed I/O for custom silicon platforms.
- Define and enforce analog layout methodologies, design rules, and best practices across the physical design team.
- Drive parasitic-aware layout strategies to meet stringent noise, matching, signal integrity, and power requirements for mixed-signal designs.
- Collaborate with circuit designers to translate schematic intent into optimized physical implementations, iterating on layout-versus-schematic and parasitic extraction results.
- Own physical verification closure, including DRC, LVS, antenna checks, and sign-off readiness across advanced process nodes.
- Establish floorplanning and integration strategies for analog IP blocks within larger mixed-signal SoC contexts.
- Provide technical guidance and layout direction to engineers and contractors, reviewing layouts and driving consistency in methodology, quality, and schedule execution.
- Partner with process technology and design kit teams to evaluate new process nodes, contribute to PDK qualification, and resolve layout-induced performance issues through post-layout simulation analysis.
- Own long-term physical design roadmaps and methodology investments that scale across multiple silicon programs.
Qualifications
- Bachelor’s degree in Electrical Engineering, Computer Engineering, relevant technical field, or equivalent practical experience.
- 8+ years of experience in full-custom analog and mixed-signal layout for production silicon in advanced CMOS process nodes, preferably 28nm or below.
- 8+ years of hands-on experience with industry-standard layout tools such as Cadence Virtuoso for schematic-driven layout, parasitic extraction, and physical verification.
- Experience leading layout of high-performance analog blocks such as PLLs, voltage regulators, data converters, or high-speed interfaces from concept through tape-out.
- Experience defining and implementing layout methodologies for matching, shielding, noise isolation, and signal integrity in mixed-signal environments.
- Experience collaborating with circuit design teams to interpret simulation requirements and translate them into layout constraints, implementation decisions, and verification closure.
- Experience managing, mentoring, and reviewing the work of layout engineers while coordinating deliverables with external contractors.
Skills
Required:Analog layoutLayout tooling (Cadence Virtuoso)Parasitic extractionDRC/LVS/antenna checksFloorplanning and integrationMentoring and leadership
Benefits
- Competitive salary commensurate with experience
- Comprehensive benefits package including health insurance
- Professional development opportunities and certification support
- Access to cutting-edge technology and cloud platforms
- Collaborative work environment with cross-functional teams
- Innovate with a Silicon Valley headquartered team, change the world
- Lumilens is an equal opportunity employer. All qualified applicants will receive consideration without regard to race, color, religion, gender, identity, orientation, veteran status, disability, or any other legally protected status.
Last updated Sep 5, 2026. Interested? Apply on the company site.
About Lumilens
Connectivity Platform for AI
Lumilens provides next-gen photonic interconnects for massively scaling out – and scaling up – AI compute infrastructure.
Photonic InterconnectsNext-Gen ManufacturingSystem-level knowledgeLumicore platformCPO/SiPh manufacturing
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