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Lead RTL Designer (PPA Experience)

Fractile· Silicon
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Hybrid (London or Bristol)$0Posted 1mo ago

About the role

Lead RTL Designer focused on datapath PPA optimization for AI/ML accelerator hardware, with full ownership from RTL to physical design collaboration. London or Bristol.

Responsibilities

  • Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets
  • Experience with low-power design techniques
  • Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths
  • Familiarity with synthesis tools (e.g. Synopsys Design Compiler/Fusion Compiler, Cadence Genus) and datapath IP/generator libraries (e.g. DesignWare)
  • Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon
  • Experience with formal verification or equivalence checking
  • Physical design awareness sufficient to collaborate effectively with PD engineers on PPA closure
  • Strong datapath microarchitecture background: pipelining, retiming, and parallelism-vs-area trade-offs for PPA
  • Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets
  • Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design
  • Deep understanding of PPA trade-off analysis, and the ability to translate PPA targets into concrete RTL and microarchitectural decisions
  • Experience with AI/ML accelerator datapath or high-performance compute chip architectures (Nice to Have)
  • Experience with static timing analysis tools (Nice to Have)
  • Export controls awareness and compliance information per role description

Qualifications

  • Strong datapath microarchitecture background: pipelining, retiming, and parallelism-vs-area trade-offs for PPA
  • Track record of driving datapath PPA closure end-to-end: identifying bottlenecks, proposing RTL changes, and validating impact against targets
  • Good knowledge of fixed-point, floating-point, and/or quantized arithmetic design
  • Deep understanding of PPA trade-off analysis, and the ability to translate PPA targets into concrete RTL and microarchitectural decisions
  • Experience with low-power design techniques
  • Experience writing timing-aware datapath RTL and iterating against synthesis/STA feedback to close timing on critical paths
  • Familiarity with synthesis tools (e.g. Synopsys Design Compiler/Fusion Compiler, Cadence Genus), and datapath IP/generator libraries (e.g. DesignWare)
  • Demonstrated, measurable PPA improvements delivered on production datapath or compute silicon
  • Experience with formal verification or equivalence checking
  • Physical design awareness sufficient to collaborate effectively with PD engineers on PPA closure

Skills

Required:Datapath RTL designPPA analysis and optimizationSynthesis toolsFixed-point / Floating-point / Quantized arithmeticFormal verification / Equivalence checkingCollaboration with PD/Physical design
Nice to have:Low-power design techniques

Benefits

  • Competitive salary
  • Equity & Ownership
  • Private Medical, Dental and Vision
  • Contributory Pension
  • 25 Days holiday plus bank holidays
  • Life/Critical Illness Insurance
  • Diverse & fun office environment
Last updated Sep 10, 2026. Interested? Apply on the company site.
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About Fractile

Radically Accelerate Frontier Model Inference

Fractile is designing AI compute systems that will enable the next generation of AI scaling: frontier model inference, 25x faster, at 1/10th the cost.

frontier model inferenceAI computecompute systemsAI scalinginference hardwareprocessor innovation
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